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advanced information linear technology / dust networks smartmesh ? wirelesshart tm ltp5901/LTP5902-whm 2.4 ghz 802.15.4 eterna tm mote module about smartmesh wirelesshart smartmesh wirelesshart products are designe d for the harshest industrial environments, where low power, reliability, resilience and scalability are key. smartmesh wirelesshart solutions are well-su ited for applications requiring wirelesshart standards complia nce, as well as a wide range of applica tions from renewable energy generation, such as solar and wind power, to factory machine health monitoring and data center hvac energy management. smartm esh wirelesshart complies w ith the wirelesshart (iec 62591) standard, offers the lowest power consump tion in its class and is the most widely used wirelesshart produc t available. smartmes h wirelesshart systems are easy for industrial automation ve ndors to integrate and simple for end users to deploy. product descriptions ? ltp5901/LTP5902-whm the ltp5901/LTP5902-whm mote module combines dust networks? robust sensor networking solution with dust?s breakthrough eterna tm soc technology in an easy-to-integrate 22-pin module, and may serve as a drop-in replacement for dust networks? m2510 mote module. as part of the smartmesh wirele sshart system, the ltp5901/LTP5902-whm enables customers to integrate a standards-based wireless network into sensors and actuators to provide scalable bidire ctional communications. the ltp5901/LTP5902-whm is designed for use in line-powered, battery-pow ered, or energy-scavenging sensor and actuator applications that demand reliable performance and ultra-low power operation. with dust networks? innovative ieee 802.15.4-compl iant design and integrated power amplifier, the ltp5901/LTP5902-whm enables a decade of ba ttery life on two aa batteries, including routing motes. all motes function as wireless routers, enabling a redundant, high performance, full-mesh topology. the ltp5901/LTP5902-whm mote modules combin e dust networks? robust sensor networ king solution with dust?s breakthrough eterna tm soc technology in an easy-to-integrate surface-mount printed circuit board (p cb). the ltp5901-whm module includes an on- board chip antenna, while the LTP5902-whm module incl udes an mmcx antenna conn ector. both pcb modules will come with modular certifications for fcc, ce, and ic. to acce lerate customer development time and reduce development costs, dust networks provide s a fully engineered rf solution, comprehensive apis, and complete development documentation. key product features highly scalable ? automatic network formation?new motes join automatically from anywhere in the network ? all motes are wireless routers, providing a full-mesh network that easily sc ales to tens of thousands of motes per square kilometer ? time-synchronized communication across 15 channels virtually eliminates in-network collisions, allowing for dense deployments in overlapping radio space superior reliability ? intelligent networking platform enables greater than 99.99% network reliability ev en in the most challenging monitoring and control environments ? time-synchronized channel hopping seamlessly compensates for in band blocking and multipath fading in dynamic rf environments wirelesshart (iec62591) compliance ? interoperable with wirelesshart devices ultra-low power operation ? industry-leading radio technology capable of line-powered, battery-powered, or energy-scavenging operation ? automatic power optimization of every device in network, enabling a decade of network operation on two lithium aa batteries easy to integrate and deploy ? fully engineered rf, with power amplifier (pa), balun, and antenna matching circuitry ? a comprehensive application programming interface (api) provides a rich and flexible f unctionality to ease software development and device integration secure global market solution ? operates on 2.4 ghz global license-free band, providing customers with a single product for world-wide use ? rf modular certifications (pending)-fcc, ic, and ce ? aes-128 bit encryption ieee 802.15.4e mac encryption and authentication ieee 802.15.4 phy rssi
advanced information 2 linear technology / dust networks eterna datasheet table of contents 1.0 general ..............................................................................................................4 1.1 related docume ntation ..................................................................................... 4 1.2 conventions..................................................................................................... 4 1.2.1 signal naming .............................................................................................. 4 1.2.2 number format ............................................................................................ 4 2.0 introduction .......................................................................................................5 2.1 power supply ................................................................................................... 5 2.1.1 supply monitoring and reset .......................................................................... 6 2.2 precision timing ............................................................................................... 6 2.2.1 time synchronization .................................................................................... 6 2.3 time refe rences............................................................................................... 6 2.3.1 relaxation o scillator...................................................................................... 6 2.3.2 32.768 khz crystal ....................................................................................... 6 2.3.3 20 mhz crystal ............................................................................................. 6 2.4 radio .............................................................................................................. 6 2.5 uarts............................................................................................................. 7 2.5.2 api uart pr otocol......................................................................................... 7 2.5.3 cli uart..................................................................................................... 8 2.6 autonomous mac ............................................................................................. 8 2.7 security .......................................................................................................... 8 2.8 temperature sensor ......................................................................................... 8 2.8.1 radio inhibit ................................................................................................ 8 2.8.2 sleep .......................................................................................................... 9 2.10 flash programming ........................................................................................... 9 3.0 9 4.0 operation ...........................................................................................................9 4.1 start up .......................................................................................................... 9 4.1.1 fuse table ..................................................................................................10 4.2 serial flash emulation ......................................................................................10 4.3 operatio n .......................................................................................................10 4.3.1 active state ................................................................................................10 4.3.2 doze state..................................................................................................10 4.4 duty cycling and autono mous periph erals...........................................................11 5.0 pinout ..............................................................................................................12 5.2 eterna mote modules........................................................................................12 5.3 power supply ..................................................................................................15 5.3.1 antenna .....................................................................................................15 5.4 analog ...........................................................................................................15 5.5 jtag..............................................................................................................15
advanced information eterna datasheet linear technology / dust networks 3 6.0 absolute maximum ra tings ..............................................................................16 7.0 recommended oper ating conditions................................................................17 8.0 electrical characteristics ..................................................................................17 8.1 radio specif ications .........................................................................................17 8.2 dc characteristics ...........................................................................................17 8.3 radio receive char acteristics ............................................................................18 8.4 radio transmitter ch aracterist ics.......................................................................19 8.5 digital i/o char acterist ics .................................................................................19 8.6 temperature sensor characteri stics ...................................................................20 8.7 adc characte ristics .........................................................................................20 8.8 system charac teristics .....................................................................................20 8.9 uart ac charac teristics ...................................................................................21 8.10 timen ac charac teristics ..................................................................................22 8.11 sleepn ac char acterist ics ................................................................................22 8.12 radio_inhibit ac ch aracterist ics.....................................................................22 8.13 flash ac charac teristics..................................................................................23 8.14 flash programming ac characteri stics ................................................................23 9.0 typical performance characteristics ................................................................24 10.0 mechanical details ...........................................................................................25 10.2 mote module ...................................................................................................25 10.3 soldering info rmation ......................................................................................27 11.0 regulatory and standard s compliance .............................................................27 11.1 compliance to restriction of ha zardous substanc es (roh s) ...................................27 12.0 references .......................................................................................................27 13.0 order information............................................................................................27
advanced information 4 linear technology / dust networks eterna datasheet 1.0 general 1.1 related documentation ? 040-0102 eterna integration guide ? 040-0109 design specific configuration guide ? 040-0110 eterna serial programmer guide 1.2 conventions 1.2.1 signal naming the naming convention for eterna signals is upper_case_separated_by_underscore. active-low signals, such as resetn, add a trailing lower case n. an exception to the naming convention is uart transmit and receive signals which are named consistent with industry practice as rx and tx, om itting the lower case n, despite being active low signals. the terms assertion and active refers to a signal in a logically true state: logic ?1? for active hi gh signals and logic ?0? for ac tive low signals. the terms negated and inactive refer to a signal being in its logically false state: logic ?0? for active high si gnals and logic ?1? for active low signals. 1.2.2 number format the 0x prefix indicates a hexadecimal number follows. the 0b prefix indicates a binary number follows. the lack of a prefix indicat es a decimal number follows.
advanced information eterna datasheet linear technology / dust networks 5 2.0 introduction eterna is the world?s most energy-effi cient ieee 802.15.4 compliant platform enabling battery and energy harvested endpoint, routing and network management solutions. with a powerful 32-bit arm ? cortex?-m3, best in class radio, flash, ram and purpose-built peripherals, eterna provides a flexible, scalable and robust networking solution for applications demanding both minimal energy consumption and data reliability in even the most challenging rf environments. shown in figure 1, eterna integrates purpose-built peripheral s that excel in both low operating-energy consumption and the ability to rapidly and precisely cycle between operating and low-po wer states. items in the shaded region correspond to the analog/rf components. cortex-m3 timers sched. auto mac aes flash 512 kb flash controller 802.15.4 framing dma 802.15.4 mod 802.15.4 demod api uart (6-pin) ipcs spi slave ptat pmu / clock control bat. load sram 72 kb code system lna pa bpf ppf pll rssi lpf 20 mhz s analog regulator clock regulator core regulator voltage reference primary dc/dc converter pa dc/dc converter por 32 khz adc ctrl. 10-bit adc relaxation oscillator 32 khz, 20 mhz 4-bit dac vga cli uart (2 pin) limiter adc dac agc figure 1 eterna block diagram 2.1 power supply eterna is powered from a single pin, vsupply, which powers th e i/o cells and is also used to generate internal supplies. eterna?s two on-chip dc/dc converters minimize eterna?s energy consumption while the device is awake. to prevent power from being wasted the dc/dc converter is disabled when the device is in low-power state. eterna?s rejection of supply noise is substantial owing to the two integrated dc/dc converters an d three integrated low-dropout regulators. eterna?s operating supply range is high enough to support direct connection to li-sclo 2 sources and wide enough to support battery operation over a broad temperature range.
advanced information 6 linear technology / dust networks eterna datasheet 2.1.1 supply monitoring and reset eterna integrates an power on reset (por) circuit and as the re setn input pin is nominally configured with an internal pull- up resistor, thus no connection is required. for a graceful shutdown, the software and networking layers be cleanly halted prior to assertion of the resetn pin. eterna includes a soft brown-out monitor that fully protects the flash from corruption in the event that power is removed while writing to flash. inte grated flash supervisory functionality in conjunction with *** (do we do a jfs?) yields a robust non-volatile file system. 2.2 precision timing eterna, differs from competing 802.15.4 product offerings by providing low-power dedicated timing hardware and timing algorithms that provide timing precision two to three orders of magnitude better than any other available low-power solution. improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception thereby lowering even further the power consumed by an eterna network. eterna?s patented timing hardware and timing algorithms provide superior performance over rapid temperatur e changes, further differentia ting eterna?s reliability when compared with other wireless products. in addition, precise timing enables networks to reduce spectral dead time, increasing total network throughput. 2.2.1 time synchronization in addition to coordinating timeslots across the network, whic h is transparent to the user, eterna?s unparalleled timing management is used to support two mechanisms to share network time. having an accurate, shared, network-wide time base enables events to be accurately time stamped or tasks to be performed in a synchronized fash ion across a network. eterna will send a time packet through its serial interface when one of the following occurs: ? eterna receives an hdlc request to read time ? the timen signal is asserted the use of timen has the advantage of being more accurate. th e value of the timestamp is captured in hardware relative to the rising edge of timen. if the hdlc request is used, due to packet processing the value of the timestamp may be captured several milliseconds after receipt of the packet. see section 8.10 for the time functions definition and specifications. 2.3 time references eterna includes three clock sources: a low power oscillator designed for a 32.768 khz crystal, the radio reference oscillator designed for a 20 mhz crystal, and an internal relaxation oscillator. 2.3.1 relaxation oscillator the relaxation oscillator is the primary clock source for eterna, providing the clock for the cpu, memory subsystems, and all peripherals. the internal relaxation oscillator typically starts up in a few s, providing an expedient, low-energy method for duty cycling between active and low power states. quick start-up from the doze state, defined in section 4.0, allows eterna to wake up and receive data over the uart and spi interfaces by simply by detecting activity the appropriate signals. 2.3.2 32.768 khz crystal once eterna is powered up and the 32.768 khz crystal source ha s begun oscillating, the 32.768 khz crystal remains operational while in the active state, and is used as the timing basis when in doze state. see section 4.0 for a description o f eterna?s operational states. 2.3.3 20 mhz crystal the 20 mhz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by eterna as needed. 2.4 radio eterna is the lowest-power commercially available 2.4 ghz ieee 802.15.4e radio by a substantial margin. (please refer to section 8.2 for power consumption numbers.). eterna?s integrated power amplifier is calibrated and temperature-compensated to consistently provide power at a limit suitable for worldwid e radio certifications. additionally, eterna uniquely includes a
advanced information eterna datasheet linear technology / dust networks 7 hardware-based autonomous mac that handles precise sequencing of peripherals, including the transmitter, the receiver, and aes peripherals. the hardware-based autonomous mac minimizes cpu activity, thereby further decreasing power consumption. 2.5 uarts the principal network interface is th rough the application programming inte rface (api) uart. a command-line interface (cli) is also provided for support of test and debug functions. both uarts sense activity continuously, consuming virtually no power until data is transferred over the port and then automatically returning to their lowest power state after the conclusion of a transfer. 2.5.2 api uart protocol eterna?s api uart operates in mode 4, incorporating optional flow control, at 115200 baud. packets are hdlc encoded with one stop bit and no parity bits. the flow control signals for eterna?s api receive path are shown in figure 5. if the fl ow control signals are used (recommended) tr ansfers are initiated from a companion processor by asserting uart_rx_rtsn. eterna responds by asserting uart_rx_ctsn. if flow control is used, after detecting the assertion of uart_rx_ctsn the companion processor may send the entire packet. following the tr ansmission of the final byte in the packet the companion processor negates uart_rx_rtsn and waits until the nega tion of uart_rx_ctsn befo re asserting uart_rx_rtsn again. flow control automatically ensures compliance with inter-packet delay requirements, so explicit delay-checking is not required. if flow control is not desired or needed it may be disabled by tying uart_rx_rtsn high. when flow control is not used the companion processor may send the entir e packet; in this case the companion processor must comply with the minimum inter-packet delay as defined in section 8.9. figure 5 uart mode 4 receive flow control uart mode 4 also incorporates level-sensitive flow control for eterna uart transmissions on the uart tx pin. packets are hdlc encoded with one stop bit and no parity bits. the flow control signals for tx are shown in figure 6. a transfer request is signaled by eterna device asserting uart_tx_rtsn. the uart_tx_ctsn signal may be actively driven by the companion processor when it is ready to receive a packet or it may be tied low if the companion processor will always be ready to receive a packet. after detecting a logic ?0? on uart_tx_ctsn eterna sends the entire packet. following the transmission of the final byte in the packet eterna negates uart_tx_rtsn and waits for a minimum period (what is the period called?) defined in section 8.9 before asserting uart_tx_rtsn again (if a packet needs to be transmitted)
advanced information 8 linear technology / dust networks eterna datasheet figure 6 uart mode 4 transmit flow control for details on the timing of the uart protocol , see section 8.9 (uart ac characteristics). 2.5.3 cli uart the command line interface (cli) uart port is a two wire protocol (tx and rx) that operates at a fixed 9600 baud rate with one-stop bit and no parity. the cli uart interface is in tended to support command-line instructions and response activity. 2.6 autonomous mac eterna was designed as a system solution with the objective of providing a reliable, ultra-low power, and secure network. a reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too complex to completely support through hard ware acceleration alone. as described in section 2.2, proper time management is essential for optimizing a solution that is both low power an d reliable. to address this solution eterna includes the autonomous mac, which includes hardware support for c ontrolling all of the time-critical radio operations. the autonomous mac provides two benefits: first, preventing va riable software latency from affecting network timing and second, greatly reducing system power consumption by allowing the cpu to remain inactive during the majority of the radio activity. the autonomous mac, unique to eterna, provides software-independent timing control of the radio and radio- related functions, resulting in superior reliability and exceptionally low power. 2.7 security network security is an often overlooked component of a complete network solution. proper implementation of security protocols is significant in terms of both engineering effort and market value in an oem product. eterna system solutions provide a fips-197 validat ed encryption scheme, an d goes further, providing a complete set of mechanisms to protect network security. eterna includes hardwa re support for electronica lly locking devices, thereby preventing access to eterna?s flash and ram memory. this lock-out feature provides a means to securely unlock a device should support of a product require access. for details see 040-0109 design specific configuration guide. 2.8 temperature sensor eterna includes a calibrated temperature sensor on chip. the temperature readings are availa ble locally through eterna?s serial api, in addition to being available via the network mana ger. the performance characteristics of the temperature sensor can be found in section 8.6. 2.8.1 radio inhibit the radio_inhibit digital interrupt enables an external contro ller to temporarily disable the radio software drivers (for example, to take a sensor reading that is susceptible to ra dio interference). when radio_inhibit is asserted the software radio drivers will disallow radio op erations including clear channe l assessment, packet transmits, or packet receipts. if a rad io event is in progress radio inhibit will take effect after the present operation completes. for details on the timing associate d with radio_inhibit, see section 8.12.
advanced information eterna datasheet linear technology / dust networks 9 2.8.2 sleep the sleepn digital interrupt enables an ex ternal controller to temporarily disable eterna?s duty cycling between active and doze states (see section 4.0 for state definitions). forcing eterna to the doze state should only be done when absolutely necessary, such as when taking a very sensitive sensor read ing, as forcing a device into a doze state will on the average increase the energy consumption of other devices in the networ k. when sleepn is asserted th e software will go into a doze state until the sleepn signal is negated. for details on the timing associated with sleepn, see section 8.11. 2.10 flash programming eterna?s software images are loaded vi a the ipcs, in-circuit programming contro l system, spi interf ace. sequencing of resetn and flash_p_enn, as de scribed in section 4.0, places eterna in a state emulating a serial flash to support in- circuit programming. hardware and software for supporting development and production programming of devices is described in 040-0110 eterna serial programmer guide. the serial protocol, spi, and timing parameters are described in section 8.13. 4.0 operation in order to provide capabilities and flexibility in addition to ultra low power, eterna operates in various states, as shown in figure 8 and described in this section. cpu and peripherals inactive resetn low and flash_p_enn low lowpowersleep command operation set resetn high and flash_p_en high for 125 s, then set resetn low load fuse settings serial flash emulation reset doze deep sleep active power-on reset start up inactive hw or pmu event resetn low and flash_p_enn high vsupply > por de-assert resetn boot assert resetn assert resetn assert resetn figure 8 state diagram ? operating modes 4.1 start up start up occurs as a result of either tripping of the power-on -reset circuit or the assertion of resetn. after the completion of power-on-reset (see section 2.1.1) or the falling edge of an internally synchronized resetn, eterna loads its fuse table (see section 4.1.1), including setting i/o direction. in this state, eterna checks the state of the flash_p_enn and resetn
advanced information 10 linear technology / dust networks eterna datasheet and enters the serial flash emulation mode , if both signals are asserted. if the flas h_p_enn pin is not asserted but resetn is not asserted, eterna automatically reduces its energy consumption to a minimum until resetn is released. once resetn is de- asserted, eterna goes through a boot sequence, an d then enters the active state. 4.1.1 fuse table eterna?s fuse table is a 2 kb page in flash that contains two data structures, one for hardware configuration immediately following power on reset or the assertion of resetn and one for configuration of design specific parameters. hardware support for configuration includes configuration of i/o, preventing i/o leakage from negatively affecting current consumption during power on, which can be a significant issue for current limited supplies. examples of design-specific parameters include setting of uart modes, clock sources and tr im values. fuse tables are created via the fuse table application software described in 040-0109 design specific confi guration guide. fuse tables are loaded into flash using the same software and in-circuit programmer used to load eterna?s networking software image ? see the 040-0110 eterna serial programmer guide for details. 4.2 serial flash emulation when both resetn and flash_p_enn are asserted, eterna di sables normal operation and enters a mode to emulate the operation of a serial flash. in this mode, its flash can be pr ogrammed with software updates . for details, see section 2.10. 4.3 operation once eterna has completed startup, eterna transitions to the operational group of states ( active / cpu active, active / cpu inactive, and doze). there, eterna cycles between the various states, automatically selecting the lowest power state possible while fulfilling the demands of network operation. 4.3.1 active state in active state, the eterna?s relaxation oscillator is runnin g and peripherals are enabled as needed. the arm cortex-m3 cycles as needed between cpu-active and cpu-inactive (referred to in the arm co rtex-m3 literature as ?sleep now? or ?sleep on exit? modes). eterna?s extensive use of dma and intelligent peripherals that can independently move eterna between the active and doze states mini mizes the time the cpu is active, significantly reducing eterna?s energy consumption. 4.3.2 doze state the doze state consumes orders of magnitude less current than the active state (see table 6) and is entered when all of the peripherals, save the low power portion of the timer module, and the cpu are inactive. in the doze state eterna?s full state is retained and eterna is configured to detect, wake, and rapidly respond to activity on i/os (such as uart signals and the timen pin). the doze state also us es the 32.768-khz oscillator and 32 khz based timers are active.
advanced information eterna datasheet linear technology / dust networks 11 4.4 duty cycling and autonomous peripherals eterna?s ability to quickly and efficiently transition betwee n doze and active states, in conjunction with the ability of peripherals to operate autonomously for most operations (sho wn in figure 9), enables the system solution to significantly reduce power consumption. for example the system can automatically go from doze to active and determine if rf energy is present. the cpu is then only woken if a packet is detected, otherwise eterna returns to doze mode. figure 9 low energy duty cycling
advanced information 12 linear technology / dust networks eterna datasheet 5.0 pinout 5.2 eterna mote modules the eterna mote modules are shown in figure 11 and figure 12. pins are described in table 2, where they are grouped by function. in some cases, a pin may have multiple possible functions. note: all unused input pins not configured with a pull resistor (see pull column in pin out table) must be driven to an inactive state to avoid excess leakage and undesired operation. leakage due to floating inputs can be substantially greater than eterna?s average power consumption. 30 gnd 29 nc 28 dp0 27 sleepn 26 dp2 / gpio21 25 dp3 24 reserved 23 reserved 22 reserved 21 dp4 20 gnd 19 tck 18 tms 17 tdo 16 tdi 15 resetn 14 nc 13 nc 12 reserved 11 gnd 10 ai_0 9 ai_3 8 ai_1 7 ai_2 6 radio_txn 5 radio_tx 4 lna_en 3 nc 2 reserved 1 gnd 37 gnd 38 spim_miso 39 ipcs_ssn / gpio3 40 spim_mosi 41 spim_sck 42 gnd 43 spim_ss_1n 44 spim_ss_0n 45 dp1 46 pwm0 47 spis_miso 48 gpio26 / spis_mosi 49 spis_sck 50 spis_ssn 51 flash_p_enn 52 nc 53 nc 54 reserved 55 vsupply 56 gnd 57 uart_rx_rtsn 58 uart_rx_ctsn 59 uart_rx 60 uart_tx_rtsn 61 uart_tx_ctsn 62 uart_tx 63 timen 64 radio_inhibit 65 nc 66 gnd antenna connector figure 11 LTP5902-whm ? mote module with mmcx antenna connector
advanced information eterna datasheet linear technology / dust networks 13 figure 12 ltp5901-whm ? mote module with chip antenna
advanced information 14 linear technology / dust networks eterna datasheet table 2 eterna mote module pinout assignments mechanical na mech contacts for mechan ical support of mmcx connector no power supply type i/o pull description 1 gnd power - - ground 11 gnd power - - ground 20 gnd power - - ground 30 gnd power - - ground 34 gnd power - - ground 37 gnd power - - ground 42 gnd power - - ground 56 gnd power - - ground 66 gnd power - - ground 55 vsupply power - - module power supply input no radio type i/o pull description 4 lna_en 1 o - external lna enable gpio17 1 i/o - general purpose digital i/o 5 radio_tx 1 o - radio tx active (external pa enable/switch control) gpio18 1 i/o - general purpose digital i/o 6 radio_txn 1 o - radio tx active (external pa enable/switch control), active low gpio19 1 i/o - general purpose digital i/o 64 radio_inhibit 1* i - radio inhibit gpio15 i/o - general purpose digital i/o no analog type i/o pull description 10 ai_0 analog i - analog input 0 8 ai_1 analog i - analog input 1 9 ai_3 analog i - analog input 3 7 ai_2 analog i - analog input 2 no general type i/o pull description 15 resetn 1 i up reset, input, active low no jtag type i/o pull description 16 tdi 1 i up jtag test data in 17 tdo 1 o - jtag test data out 18 tms 1 i up jtag test mode select 19 tck 1 i down jtag test clock no cli type i/o pull description 31 uartc0_tx 2 o - cli uart 0 transmit 32 uartc0_rx 1 i up cli uart 0 receive no uart type i/o pull description 57 uart_rx_rtsn 1* i - uart receive (rts) request to send, active low 58 uart_rx_ctsn 1 o - uart receive (cts) clear to send, active low 59 uart_rx 1* i - uart receive 60 uart_tx_rtsn 1 o - uart transmit (rts) request to send, active low 61 uart_tx_ctsn 1* i - uart transmit (cts) clear to send, active low 62 uart_tx 2 o - uart transmit
advanced information eterna datasheet linear technology / dust networks 15 no ipcs spi / flash programming type i/o pull description 33 ipcs_miso 2 o - spi flash emulation (miso) master in slave out port gpio6 i/o - general purpose digital i/o 35 ipcs_mosi 1 i - spi flash emulati on (mosi) master out slave in port gpio5 i/o - general purpose digital i/o 36 ipcs_sck 1 i - spi flash emulation (sck) serial clock port gpio4 i/o - general purpose digital i/o 39 ipcs_ssn 1 i - spi flash emulation slave select, active low gpio3 i/o - general purpose digital i/o 51 flash_p_enn i up flash program enable, active low note that this functionality is av ailable only when resetn is asserted no special purpose digital type i/o pull description 27 sleepn 1* i - deep sleep, active low 63 timen 1* i - time capture request, active low * input signals that must be driven or pulled to a valid state to avoid leakage. 5.3 power supply eterna is powered from a single pin, vsupply, and generate s all required supplies internally. with two integrated dc/dc converters and four voltage regulators, the sensitivity to nois e on vsupply is minimal. howe ver, during typical operation eterna will vary its load on the power supply from the a range to 10?s of ma over a few s. during such transients, the power supply must meet the specifications for supply noise tolerance. eterna is designed to operate with specific decoupling capacitance on vcore, vdda, vosc, vddpa, and vprime, as well as the internal converter capacitors c1 through c4. failure to use correctly sized ceramic capacitors can result in supply instability and performance degradation. 5.3.1 antenna eterna allows direct connection to a single-ended 50-ohm ante nna; an internal tx/rx switch simplifies external circuitry requirements. because both the transmit a nd the receive paths are single-ended, a balun (with its associated cost and efficiency loss) are not required. eterna provides options to set typical output power to 0 dbm or to +8 dbm using the on-chip pa. for further details on radio tr ansmit and receive, see section 2.4. 5.4 analog eterna has four analog inputs. its 10-bit adc includes a 4-bit dac for adjusting offset and a 3-bit vga, as shown in figure 13. the software application layer controls adc operation and may be configured to automatically sample any combination of the internal temperature sensor, or analog input signals. figure 13 analog to digital chain 5.5 jtag eterna includes an ieee 1149.1-compliant jtag port for boundary scan.
advanced information 16 linear technology / dust networks eterna datasheet 6.0 absolute maximum ratings the absolute maximum ratings shown in table 3 should not be violated under any circumstances. permanent damage to the device may be caused by exceeding one or more of these parameters. unless otherwise noted, all voltages in table 3 are relative to gnd. table 3 absolute maximum ratings parameter min typ max units comments supply voltage (vsupply to gnd) ?0.3 3.76 v voltage on any digital i/o pin ?0.3 vsupply + 0.3 up to 3.76 v input rf level +10 dbm i nput power at antenna connector storage temperature range ?55 +105 c extended storage at high temperature is discouraged, as this negatively affects the data retention of eterna?s calibration data. lead temperature +245 c for 10 seconds vswr of antenna 3:1 esd protection antenna pad 8000 v hbm all other pads 1000 v hbm 100 v cdm caution! esd sensitive device. precaution should be used when handling the device in order to prevent permanent damage.
advanced information eterna datasheet linear technology / dust networks 17 7.0 recommended operating conditions table 4 recommended operation conditions parameter conditions min typ max units vsupply range including noise and load regulation 2.1 3.6 3.76 v voltage supply noise requires recommended rlc filter, 50 hz to 2 mhz 250 mv p-p operating temperature range ?40 +85 c operating relative humidity non-condensing 10 90 % rh power on reset threshold 1.5 v temperature ramp -8 +8 c/min 8.0 electrical characteristics 8.1 radio specifications the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 5 detailed radio specifications parameter conditions min typ max units frequency band as specified by [ 1 ] 2.4000 2.4835 ghz number of channels 15 channel separation as specified by [ 1 ] 5 mhz occupied channel bandwidth at ?20 dbc 2.7 mhz channel center frequency where k = 11 to 25.? 2405 + 5 * (k-11) mhz modulation ieee 802.15.4 dsss raw data rate as specified by [ 1 ] 250 kbps range* indoor ? outdoor ? free space 25 c, 50% rh, +2 dbi omni-directional antenna 100 300 1200 m m m * actual rf range performance is subject to a number of inst allation-specific variables in cluding, but not restricted to ambient temperature, relative humidity, presence of acti ve interference sources, line-of-sight obstacles, and near- presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. as a result, actual performance varies. ? 1 meter above ground. ? channel 26 as specified by [ 1 ] is not used.. 8.2 dc characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 6 dc specifications parameter conditions min typ max units reset after power-on reset 1.2 a deep sleep 0.8 a doze ram on; arm cortex-m3, flash, radio, and peripherals off, all data and state retained, 32.768 khz reference active 1.2 a serial flash emulation 20 ma peak operating current system operating at 14.7 mhz radio tx flash write at +8 dbm output power 30 ma
advanced information 18 linear technology / dust networks eterna datasheet parameter conditions min typ max units at 0 dbm output power 26 ma active* arm cortex-m3, ram, and flash on; radio and peripherals off clk = 7.37 mhz, vcore = 1.8 v 2.4 ma flash write single bank write 3 ma flash erase single bank page or mass erase 2.5 ma radio tx ? mesh network - clk = 7.3728 mhz, aes active 0 dbm output power +8 dbm output power 5.4 9.7 ma ma radio rx ? mesh network - clk = 7.3728 mhz, aes active 4.5 ma note: see section 3.0 for detailed oper ational definitions of states. * clk = clock frequency of cpu and peripherals. ? current with autonomous mac handling packet transmission and reception; cpu idle. 8.3 radio receive characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 7 radio receive characteristics parameter conditions min typ max units receiver sensitivity per = 1%, as specified by [ 1 ] ?93 dbm receiver sensitivity per = 50% ?95 dbm saturation (maximum input level) 0 dbm adjacent channel rejection (high side) desired signal at -82 dbm, adjacent modulated channel at 5 mhz, per = 1%, as specified by [ 1 ] 22 dbc adjacent channel rejection (low side) desired signal at -82 dbm, adjacent modulated channel at -5 mhz, per = 1%, as specified by [ 1 ] 19 dbc alternate channel rejection (high side) desired signal at -82 dbm, adjacent modulated channel at 10 mhz, per = 1%, as specified by [ 1 ] 40 dbc alternate channel rejection (low side) desired signal at -82 dbm, adjacent modulated channel at -10 mhz, per = 1%, as specified by [ 1 ] 36 dbc second alternate channel rejection desired signal at -82 dbm, adjacent modulated channel at +/-10 mhz, per = 1%, as specified by [ 1 ] 42 dbc co-channel rejection desired signal at -82 dbm. undesired signal is 802.15.4 modulated at same frequency. per = 1%, as specified by [ 1 ] ?6 dbc lo feed through advanced information eterna datasheet linear technology / dust networks 19 8.4 radio transmitter characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 8 radio transmitter characteristics parameter conditions min typ max units output power calibrated settings delivered to a 50 ? load, over temperature and voltage ranges 0 +8 dbm dbm spurious emissions 30 mhz to 1000 mhz 1 ghz to 12.75 ghz upper band edge (peak) upper band edge (average) lower band edge conducted measurement with a 50 ? single-ended load, +8 dbm output power. all measurements made with max hold. rf implementation per eterna reference design. rbw = 120 khz, vbw = 100 hz rbw = 1 mhz, vbw = 3 mhz rbw = 1 mhz, vbw = 3 mhz rbw = 1 mhz, vbw = 10 hz rbw = 100 khz, vbw = 100 khz advanced information 20 linear technology / dust networks eterna datasheet high drive - 0.3 ? + 0.3 ? input leakage current 50 na ? min and min and max io input levels must respect the minimum and maximum voltages for vsupply. 8.6 temperature sensor characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 11 temperature sensor characteristics parameter conditions min typ max units offset temperature offset e rror at 25 oc 0.25 c slope error slope error from -40 to +85 oc 0.033 c/c 8.7 adc characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 12 adc characteristics parameter conditions min typ max units variable gain amplifier gain gain error 1 8 1 % digital to analog converter (dac) offset output differential non-linearity (dnl) 1.8/16 1.8 7.2 v mv analog to digital converter (adc) full-scale, signal resolution offset differential non-linearity (dnl) integral non-linearity (inl) settling time conversion time current consumption midscale 10-kohm source impedance 1.80 1.8 4 1 1 10 20 50 v mv lsb lsb lsb s s a analog inputs* load input resistance 17 1 35 2 pf kohm * the analog inputs to the adc can be model as a series resi stor to a load capacitor. at a minimum the entire circuit, including the source impedance for the signal driving the anal og input should be designed to settle to within ? lsb within the sampling window to match the performance of the adc. 8.8 system characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 13 system characteristics parameter conditions min typ max units doze to active state delay 5 s doze to radio tx or rx 1.2 ms q cca charge to sample rf channel start from doze state 4 c radio baud rate 250 kbps resetn pulse width 125 s
advanced information eterna datasheet linear technology / dust networks 21 8.9 uart ac characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 14 uart timing values parameter conditions min typ max unit t rx_baud deviation from baud rate ?2 +2 % t tx_baud deviation from baud rate ?1 +1 % t rx_rts_r to rx_cts assertion of uart_rx_rtsn to assertion of uart_rx_ctsn, or negation of uart_rx_rtsn to negation of uart_rx_ctsn 0 22 ms t cts_r to rx assertion of uart_rx_ctsn to start of byte 0 20 ms t eop to rx_rts end of packet (end of the last stop bit) to negation of uart_rx_rtsn 0 22 ms t tx_rts_t to tx_cts assertion of uart_tx_rtsn to assertion of uart_tx_ctsn, or negation of uart_tx_rtsn to negation of uart_tx_ctsn 0 22 ms t tx_cts_t to tx assertion of uart_tx_ctsn to start of byte 0 2 bit period t eop to tx_rts end of packet (end of the last stop bit) to negation of uart_tx_rtsn 0 1 bit period t rx_interbyte receive inter-byte delay 100 ms t tx to tx_cts start of byte to negation of uart_tx_ctsn 0 ms t interpacket transmit and receive inter-packet delay (mode 4 only) 100 ms figure 16 uart timing
advanced information 22 linear technology / dust networks eterna datasheet 8.10 timen ac characteristics the following characteristics are measured with vsupply = 3.6 v at 25 c, unl ess otherwise specified. note that the time pin must remain negated until the time packet has been received. table 15 timestamp characteristics parameter conditions min typ max unit t strobe 125 s t response from rising edge of timen 100 ms resolution see the serial api definition for getparameter +/- 1 s network-wide time accuracy stable temperature environment +/- 50 s figure 17 timestamp timing diagram 8.11 sleepn ac characteristics the following characteristics are measured with vsupply = 3.6 v at 25 c, unl ess otherwise specified. note that the time pin must remain negated until the time packet has been received. table 16 sleepn characteristics parameter conditions min typ max unit t doze from falling edge of sleepn 20 ms t sleep_strobe maximum strobe width 2 s figure 18 sleepn timing diagram 8.12 radio_inhibit ac characteristics the following characteristics are measured with vsupply = 3.6 v at 25 c, unl ess otherwise specified. note that the time pin must remain negated until the time packet has been received. table 17 radio_inhibit characteristics parameter conditions min typ max unit t radio_off from rising edge of radio_inhibit 20 ms t radio_inhibit_strobe maximum strobe width 2 s
advanced information eterna datasheet linear technology / dust networks 23 figure 19 radio_inhibit timing diagram 8.13 flash ac characteristics the following characteristics are m easured with vsupply = 3.6 v at 25 c, unless otherwise specified. table 18 flash ac timing values parameter conditions min typ max unit t 32-bit_word writing a 32-bit word 21 s t page_erase page erase 21 ms t mass_erase bank erase 21 ms 8.14 flash programming ac characteristics the following characteristics are measured with vsupply = 3.6 v at 25 c with 10 pf load capacitance, unless otherwise specified. table 19 spi slave ac timing values parameter conditions min typ max unit t sss ipcs_ssn setup to leading edge of ipcs_sck 15 ns t ssh ipcs_ssn hold from trailing edge of ipcs_sck 15 ns t ck ipcs_sck period 50 ns t dis ipcs_mosi data setup 15 ns t dih ipcs_mosi data hold 5 ns t dov ipcs_miso data valid 3 15 ns t off ipcs_miso data tri-state 0 15 ns figure 20 flash programming slave timing
advanced information 24 linear technology / dust networks eterna datasheet 9.0 typical performance characteristics network motes typically route through at least two parents traffic destined for the manager. the bandwidth and keep-alive overhead required to support network motes will be shared across all of the mote's parents. the supply current plots include a parameter called traffic-weighted descendants. in these graphs the term traffic-weighted descen dants refers to an amount of activity equivalent to the number of descendants were all of the network traffic and keep-alives directed to the mote in question. generally the number of descendants of a parent is more (typically 2x or more) than the number of traffic-weighted descendants. for example, with reference to figure 25 mote p1 has 0.75 traffic-weighted descendants. to obtain this value notice that mote d1 routes half its packets through mote p1 adding 0.5 to the traffic-weighted descendant value; the other half of d1's traffic is routed through its other parent, p2. mote d2 routes half its packets through mote d1 (the other half going through parent p3), which we know routes half its packets to mote p1, adding another 0.25 to the traffic-weighted descendant value for a total traffic-weighted descendant value of 0.75. figure 25 network graph depicting traffic weighted descendant value calculation the following plots correspond to networks with a p2 bandwidth profile, an assumed path stability of 80%, an 80 byte packet and unless otherwise specified operation at 25 degrees c.
advanced information eterna datasheet linear technology / dust networks 25 10.0 mechanical details 10.2 mote module the eterna mote modules comes in 66-lead, 1 mm lead pitch castellated pcb, as illust rated in figure 27 and in figure 28. figure 27 mechanical drawing ? ltp5901
advanced information 26 linear technology / dust networks eterna datasheet figure 28 mechanical drawing ? LTP5902
advanced information eterna datasheet linear technology / dust networks 27 10.3 soldering information eterna is suitable for both eutectic pbsn and rohs-6 refl ow. the maximum reflow soldering temperature is 260 oc. 11.0 regulatory and standards compliance ltp5901 is compliant with eu, fcc and ic radio frequency re gulations. for specific information on regulations, test procedures, and labeling requirements, s ee the ?ltp5901 regulat ory user guide?. LTP5902 is compliant with eu, fcc and ic radio frequency re gulations. for specific information on regulations, test procedures, and labeling requirements, s ee the ?LTP5902 regulat ory user guide?. 11.1 compliance to restriction of hazardous substances (rohs) restriction of hazardous substances (roh s) is a directive that places maximum c oncentration limits on the use of cadmium (cd), lead (pb), hexavalent chromium (cr+6), mercury (hg), polybrominated biphenyl (pbb), and polybrominated diphenyl ethers (pbde). dust networks is committed to meeting the re quirements of the european community directive 2002/95/ec. this product has been specifically designed to utilize rohs-c ompliant materials and to eliminate or reduce the use of restricted materials to comply with 2002/95/ec. the rohs-compliant design features include: ? rohs-compliant solder for solder joints ? rohs-compliant base metal alloys ? rohs-compliant precious metal plating ? rohs-compliant cable assemblies and connector choices ? lead-free qfn package ? halogen-free mold compound ? rohs-compliant and 245 c re-flow compatible note: customers may elect to use certain types of lead-free solder alloys in accordance wi th the european community directive 2002/95/ec. depending on the type of solder paste chosen, a corresponding process change to optimize reflow temperatures may be required. 12.0 references [ 1 ] ieee std. 802.15.4-2006: wireless medium access control (mac) and ph ysical layer (phy) specifications for low-rate wireless personal area networks (lr-wpans) http://standards.ieee.org/getieee802 /download/802. 15.4-2006.pdf 13.0 order information lead free finish** part marking* package description temperature range ltp5901ipc-whma???#pbf ltp5901 66-lead (42mm x 24mm) pcb -40 c to 85 c LTP5902ipc-whma???#pbf LTP5902 66-lead (37.465mm x 24mm) pcb -40 c to 85 c ** see http://www.linear.com/ or contact your sales representative to determin e the three digit software version field, ???. for more information on lead free part ma rking, go to: http://www.linear.com/leadfree/
advanced information 28 linear technology / dust networks eterna datasheet trademarks smartmesh industrial and eterna are trademarks of dust networks, inc. the dust networ ks logo, dust, dust networks, and smartmes h are registered trademarks of dust networks, inc. the linear logo is a register ed trademark of linear technology corporation. all third-party b rand and product names are the trademarks of their respective owners and are used solely for informational purposes. arm and cortex are trademarks or registered tradem arks of arm limited in the eu and other countries. copyright this documentation is protected by united states and international copyright and ot her intellectual and industrial property law s. it is solely owned by dust networks, inc. and its licensors and is distributed under a restrictive license. this product, or any portion thereof, may not be used, copied, modified, reverse assembled, reverse compiled, reverse engineered, distribut ed, or redistributed in any form by any means without the pri or written authorization of dust networks, inc. restricted rights: use, duplication, or disc losure by the u.s. government is subject to restrictions of far 52.227-14(g) (2)(6/ 87) and far 52.227-19(6/87), or dfar 252.227-7015 (b)(6/95) and dfar 227.7202-3( a), and any and all similar a nd successor legislation and r egulation. disclaimer this documentation is provided ?as is? without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of merchantability or fitness for a particular purpose. this documentation might include technical inaccuracies or other errors. corrections and improveme nts might be incorporated in new versions of the documentation. dust networks does not assume any liability arising out of the a pplication or use of any products or services and specifically disclaims any and all liability, including without limitation cons equential or incidental damages. dust networks products are not designed for use in life support appliances, devices, or other systems where malfunction can rea sonably be expected to result in significant personal injury to the user, or as a criti cal component in any life support device or system whose failur e to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. dust networks cus tomers using or selling these products for use in such applications do so at their own risk a nd agree to fully indemnify and hold dust networks and its offic ers, employees, subsidiaries, affiliates, and distributors ha rmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or una uthorized use, even if such claim alleg es that dust networks was negligent regarding the design or manufacture of its products. dust networks reserves the right to make corrections, modifica tions, enhancements, improvements , and other changes to its produ cts or services at any time and to discontinue any product or serv ice without notice. customers should obtain the latest relevant information before p lacing orders and should verify that such information is current a nd complete. all products are sold subject to dust network's terms and conditions of s ale supplied at the time of order acknowledgment or sale. dust networks does not warrant or represent that any license, eith er express or implied, is gran ted under any dust networks pat ent right, copyright, mask work right, or other dust networks intellect ual property right relating to any combination, machine, or process in which dust n etworks products or services are used. information published by dust networks regarding third-party produc ts or services does not constitute a lice nse from dust networks to use such products or services or a warranty or endorsement thereo f. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license fr om dust networks under the pate nts or other intellectual propert y of dust networks. dust networks, inc is a wholly owned subs idiary of linear technology corporation. ? dust networks, inc. 2012. all rights reserved.
advanced information eterna datasheet linear technology / dust networks 29 last revised: march 15, 2013 document status product status definition advanced information planned or under development this datasheet contains the design specifications for product development. dust networks reserves the right to change specifications in any manner without notice. preliminary engineering samples and pre-production prototypes this datasheet contains prelimi nary data; supplementary data will be published at a later time. dust networks reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. the product is not fully qualified at this point. no identification noted full production this datasheet contains the final specifications. dust networks reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete not in production this datasheet contains specific ations for a product that has been discontinued by dust networks. the datasheet is printed for reference information only.

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